The advent of ultrahigh-speed/high-functionality semiconductor devices had spurred rapid evolution of an information-consuming and knowledge-intensive society into a global web of high-speed communication networks, as exemplified by the ubiquitous presence of radiofrequency cellular or “mobile” phones in daily activities. Naturally, the world-wide spread of such a social transformation as well as an insatiable quest for more efficient and convenient life-styles further demands yet higher-speed operation of ever-shrinking semiconductor devices integrated on a much larger scale, to realize a system-on-chip versatile architecture, which is equipped with almost every conceivable functionality. As a matter of course, to meet the above demand, the physical sizes of major components of a large scale integration (LSI) circuit, i.e., metal insulator semiconductor field effect transistors (MISFET's), or more specifically, metal oxide semiconductor field effect transistors (MOSFET's), have to be reduced accordingly. Unfortunately, however, further miniaturizing the MOSFET dimensions while speeding-up its operation is increasingly becoming a difficult task to achieve. In fact, as explained below, various technical difficulties arise from this attempt.
One of such difficulties arises from sharp decrease of threshold voltage with downscaling or shrinkage of the channel length of the MOSFET (i.e., physical length of the gate electrode), known as the short channel effect. When the threshold voltage comes to depend on the physical gate length, even a slight process variation during the gate electrode formation could result in unfavorable and uncontrollable deviation in the threshold voltage. Of course, a MOSFET with an unintended threshold voltage, that is very different from the designed value, leads to an erratic device operation. The device operation incompatible with the original intention may well totally impair the proper functionality of the entire circuit. In other words, in order to obtain a large number of identical devices, the short-channel-effect-induced sharp dependence of the threshold voltage on the physical gate length is extremely detrimental. The short-channel-effect-induced intolerance of even a minute fluctuation during the device fabrication processes makes it very difficult to manufacture an electric circuit composed of a great number of uniform and coherent components, such as a dynamic random access memory (DRAM).
From a viewpoint of its physical mechanism, this short channel effect is a result of distortion of an electric potential near the central portion of the channel region. The distortion is induced by electric fields at source/drain (S/D) electrodes. As the channel length decreases, the influence of S/D electric fields comes to reach the central portion of the channel, allowing premature channel currents to flow between S/D electrodes (i.e., reducing the threshold voltage). Hence, as widely recognized, by making the p-n junctions that forms S/D regions (i.e., S/D p-n junctions) shallower, the short channel effect can be avoided. However, simply decreasing the depth of the S/D p-n junctions causes unacceptable increase in the electrical resistances of the S/D electrodes. Obviously, it impedes high-speed transmission of electrical signals through the MOSFET, thereby totally dashing the original intention of miniaturizing the MOSFET dimensions to speed-up its operation.
One of the best ways of reducing the S/D electrode resistance is silicidation (i.e., compound formation between silicon and metal substance) of upper parts of S/D p-n junctions. The metal species that could be used for the silicidation includes cobalt (Co), titanium (Ti) and nickel (Ni). However, of these metals, Ni is the primary choice for the silicidation of fine structures employed by today's ULSI technology. This is because it is free from adverse line-width effects (i.e., resistivity increase of silicide layers when they are formed on narrow lines). In addition, the silicidation reaction between Si and Ni can be completed at a temperature as low as 450° C., which is much lower than the CoSi2 formation temperature (800° C.). Moreover, this low temperature thermal treatment produces a layer of NiSi, which has a very low resistivity. However, caution is advised because applying yet additional thermal processing at a higher temperature of about 750° C. causes an unfavorable phase transition of the NiSi layer into a layer of NiSi2, that has a higher electrical resistivity than that of NiSi. Thus, naturally, it is the NiSi layer of low resistance that is typically used for ULSI devices.
Unfortunately, however, NiSi is not a problem-free option. In fact, its thermal stability is the greatest concern of the NiSi technology. In general, after having formed the low-resistance NiSi layer, it is indispensable to perform thermal processing at 500° C. for about 90 minutes, for example, in order to establish good electrical contact between the NiSi layer and a metal substance formed thereon. However, even this moderate thermal processing (i.e., at 500° C. for 90 min), though it is done at a temperature well below the phase transition temperature, is found to trigger a substantial burst of Ni atoms from the NiSi layer deep into the Si substrate. The Ni burst is so invasive that Ni even reaches a depth of about 140 nm.
The Ni atoms thus-infiltrated deeply into the Si substrate form gap states in the forbidden band of Si, thereby assisting or promoting leakage generation. Since this Ni burst into the Si substrate is a genuine and intrinsic characteristic inherent to NiSi, it progresses unavoidably whenever NiSi and Si are in physical contact at an elevated temperature. Obviously, once such gap states are formed at the S/D junctions, substantial leakage currents flow through the junctions into the Si substrate. Eventually, an intended functionality of the device will be completely lost (e.g., loss of data memorized in DRAM cells).
Now that the general problems associated with the silicidation technique are clarified, next, some more specific difficulties in relation to another technical option for achieving high-performance semiconductor devices will be discussed below. Nowadays, besides the above silicidation technique, in an insatiable quest for high-speed operation of MOSFET, an additional means to improve the device operation is also explored. In fact, in order to maximize the carrier mobilities, their crystal orientation dependencies are exploited. It is known that, in the case of Si, the crystal plane of highest electron mobility is a Si(100) plane, whereas the plane capable of attaining the maximum hole mobility is a Si(110) plane, as disclosed in H. Irie et al., “In-Plane Mobility Anisotropy and Universality under Uniaxial Strains in n- and p-MOS Inversion Layers on (100), (110), and (111) Si,” International Electron Devices Meeting (IEDM) Technical Digest, pp. 225-228 (2004).
A way of realizing integration of a complementary MOSFET (CMOSFET) circuitry with Si(100) surfaces for n-channel MOSFETs (n-MOSFETs) and Si(110) surfaces for p-channel MOSFETs (p-MOSFETs) is to make use of a direct silicon bonded (DSB) substrate, as taught from C. Sung et al., “High Performance CMOS Bulk Technology Using Direct Silicon Bond (DSB) Mixed Crystal Orientation Substrates,” IEDM Tech. Dig., pp. 235-238 (2005).
In the DSB technique, a single-crystal Si layer with its principal surface being a (110) plane is directly bonded over a single-crystal Si(100) substrate. Then, specific surface regions (on which n-MOSFETs are to be formed) are selectively amorphized by ion implantation. Subsequent recrystallization referring to the underlying Si(100) substrate convert the surface orientation of the n-MOSFET formation regions from Si(110) into Si(100), while p-MOSFET formation regions retain the original surface orientation of Si(110).
Obviously, by forming respective MOSFETs on the optimum crystal planes depending on its conductivity type, carrier mobilities of both n-MOSFET and p-MOSFET can be maximized at once. Thus, the operation speed of the whole CMOSFET circuit can be increased, without suffering from commonly observed slow-down due to sluggish performance of either slower type of constituent MOSFETs. Furthermore, since it dispenses with a silicon-on-insulator (SOI) substrate, both conventional circuit designs and common manufacturing processes of bulk CMOS fabrication can be directly applied to the DSB technology, without any “special” considerations otherwise needed when using SOI substrate. This makes it possible to readily fabricate DSB CMOSFET devices by using the existing fabrication facility while, at the same time, avoiding increase in manufacturing costs.
Nonetheless, the DSB technique is not a problem-free option either. Unfortunately, with the above advantages come accompanying penalties as detailed below. The direct bonding between surfaces of incompatible crystal orientations naturally gives rise to a host of crystal defects, such as dislocations, due to substantial lattice mismatching at the bonding interface. In addition, in order to amorphize and recrystallize micro- or even nano-scale regions with a precise spatial resolution, the Si bonding layer has to be very thin. Accordingly, the crystal defects residing at or near the bonding interface are located very close to surfaces on which MOSFETs are to be formed.
Since no insulative material is formed between S/D diffusion layers and the defect-infested bonding interface, the S/D p-n junctions (which should be formed in close proximity to the bonding interface) are thus very vulnerable to leakage generation. The crystal defects at the bonding interface and/or secondary defects (which are originated from the primary defects at the bonding interface and propagated therefrom towards the substrate surface) could cause unacceptable junction leakage.
In particular, when the DSB technology is combined with the silicidation technique, the junction leakage becomes an intractable problem. This is because the crystal defects in the DSB substrate can significantly enhance the diffusion of metal atoms released from the silicide layer (i.e., transient enhanced diffusion). The rapidly migrating metal atoms can easily reach the junction between S/D regions and the underlying substrate, thereby producing uncontrollable junction leakage.
Now, obviously, in order to avoid the above junction leakage, an efficient way of suppressing the release and diffusion of metal atoms from the silicide layer must be devised.
Otherwise, successful high-speed operation of miniaturized silicided MISFETs is totally unattainable.